Clocking Schemes for High-Speed Digital Systems
IEEE Transactions on Computers
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This paper considers the problem of determining an optimal clock skew schedule for a synchronous VLSI circuit. A novel formulation of clock skew scheduling as a constrained quadratic programming (QP) problem is introduced. The concept of a permissible range, or a valid interval, for the clock skew of each local data path is key to this QP approach. From a reliability perspective, the ideal clock schedule corresponds to each clock skew within the circuit being at the center of the respective permissible range. However, this ideal clock schedule is not practically implementable because of limitations imposed by the connectivity among the registers within the circuit. To evaluate the reliability, a quadratic cost function is introduced as the Euclidean distance between the ideal schedule and a given practically feasible clock schedule. This cost function is the minimization objective of the described algorithms for the solution of the previously mentioned quadratic program. Furthermore, the work described here substantially differs from previous research in that it permits complete control over specific clock signal delays or skews within the circuit. Specifically, the algorithms described here can be employed to obtain results with explicitly specified target values of important clock delays/skews with a circuit, such as for example, the clock delays/skews for I/O registers. An additional benefit is a potential reduction in clock period of up to 10%. An efficient mathematical algorithm is derived for the solution of the QP problem with &Ogr;(r3) run time complexity and &Ogr;(r2) storage complexity, where r is the number of registers in the circuit. The algorithm is implemented as a C++ program and demonstrated on the ISCAS'89 suite of benchmark circuits as well as on a number of industrial circuits. The work described here yields additional insights into the correlation between circuit structure and circuit timing by characterizing the degree to which specific signal paths limit the overall performance and reliability of a circuit. This information is directly applicable to logic and architectural synthesis.