IEEE Transactions on Computers
Optimal clock skew scheduling tolerant to process variations
DAC '96 Proceedings of the 33rd annual Design Automation Conference
LEDA: a platform for combinatorial and geometric computing
LEDA: a platform for combinatorial and geometric computing
Cycle time and slack optimization for VLSI-chips
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Clock skew scheduling for improved reliability via quadratic programming
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Timing optimization through clock skew scheduling
Timing optimization through clock skew scheduling
Proceedings of the 42nd annual Design Automation Conference
Race-condition-aware clock skew scheduling
Proceedings of the 42nd annual Design Automation Conference
Yield-Driven, False-Path-Aware Clock Skew Scheduling
IEEE Design & Test
A yield improvement methodology using pre- and post-silicon statistical clock scheduling
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A framework for statistical timing analysis using non-linear delay and slew models
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Clock period minimization with minimum delay insertion
Proceedings of the 44th annual Design Automation Conference
ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
An efficient phase detector connection structure for the skew synchronization system
Proceedings of the 47th Design Automation Conference
Online clock skew tuning for timing speculation
Proceedings of the International Conference on Computer-Aided Design
Clock skew scheduling for timing speculation
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
SmipRef: An efficient method for multi-domain clock skew scheduling
Integration, the VLSI Journal
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In nanometer technologies, process variations possess growing nonlinear impacts on circuit performance, which causes critical path delays of combinatorial circuits variate randomly with non-Gaussian distribution. In this paper, we propose a novel clock skew scheduling methodology that optimizes timing yield by handling non-Gaussian distributions of critical path delays. Firstly a general formulation of the optimization problem is proposed, which covers most of the previous formulations and indicates their limitations with statistical interpretations. Then a generalized minimum balancing algorithm is proposed for effectively solving the skew scheduling problem. Experimental results show that the proposed method significantly outperforms some representative methods previously proposed for yield optimization, and could obtain timing yield improvements up to 33.6% and averagely 17.7%.