Online clock skew tuning for timing speculation

Authors:
Rong Ye;Feng Yuan;Qiang Xu
Affiliations:
The Chinese University of Hong Kong, Shatin, N. T., Hong Kong, and Shenzhen Institutes of Advanced Technology, Chinese Academy of Sciences;The Chinese University of Hong Kong, Shatin, N. T., Hong Kong;The Chinese University of Hong Kong, Shatin, N. T., Hong Kong, and Shenzhen Institutes of Advanced Technology, Chinese Academy of Sciences
Venue:
Proceedings of the International Conference on Computer-Aided Design
Year:
2011

Citing 11
Cited 6

Clock Skew Optimization

IEEE Transactions on Computers
Cycle time and slack optimization for VLSI-chips

ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Clock skew scheduling for improved reliability via quadratic programming

ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation

Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Yield-Driven, False-Path-Aware Clock Skew Scheduling

IEEE Design & Test
A yield improvement methodology using pre- and post-silicon statistical clock scheduling

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Clock Skew Scheduling Under Process Variations

ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Statistical timing analysis driven post-silicon-tunable clock-tree synthesis

ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Timing yield driven clock skew scheduling considering non-Gaussian distributions of critical path delays

Proceedings of the 45th annual Design Automation Conference
Dynamic thermal clock skew compensation using tunable delay buffers

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Re-synthesis for cost-efficient circuit-level timing speculation

Proceedings of the 48th Design Automation Conference

On logic synthesis for timing speculation

Proceedings of the International Conference on Computer-Aided Design
On testing timing-speculative circuits

Proceedings of the 50th Annual Design Automation Conference
Post-placement voltage island generation for timing-speculative circuits

Proceedings of the 50th Annual Design Automation Conference
InTimeFix: a low-cost and scalable technique for in-situ timing error masking in logic circuits

Proceedings of the 50th Annual Design Automation Conference
Clock skew scheduling for timing speculation

DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
ForTER: a forward error correction scheme for timing error resilience

Proceedings of the International Conference on Computer-Aided Design

Quantified Score

Hi-index	0.00

Visualization

Abstract

The timing performance and yield of integrated circuits can be improved by carefully assigning intentional clock skews to flipflops. Due to the ever-increasing process, voltage, and temperature variations with technology scaling, however, traditional clock skew optimization solutions that work in a conservative manner to guarantee "always correct" computation cannot perform as well as expected. By allowing infrequent timing errors and recovering from them with minor performance impact, the concept of timing speculation has attracted lots of research attention since it enables "better than worst-case design". In this work, we propose a novel online clock skew tuning technique for circuits equipped with timing speculation capability. By observing the occurrence of timing errors at runtime and tuning clock skews accordingly, the proposed technique is able to achieve much better timing performance when compared to existing clock skew optimization solutions. Experimental results on various benchmark circuits demonstrate the effectiveness of the proposed methodology.