IEEE Transactions on Computers
Understanding retiming through maximum average-delay cycles
Proceedings of the 3rd ACM symposium on Parallel algorithms and architectures
Minimum padding to satisfy short path constraints
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Clock Period Minimization of Non-Zero Clock Skew Circuits
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Clock period minimization with minimum delay insertion
Proceedings of the 44th annual Design Automation Conference
Proceedings of the 45th annual Design Automation Conference
Co-synthesis of data paths and clock control paths for minimum-period clock gating
Proceedings of the Conference on Design, Automation and Test in Europe
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The race conditions often limit the smallest feasible clock period that the optimal clock skew scheduling can achieve. Therefore, the combination of clock skew scheduling and delay insertion (for resolving the race conditions) may lead to further clock period reduction. However, the interactions between clock skew scheduling and delay insertion have not been well studied. In this paper, we provide a fresh viewpoint to look at this problem. A novel approach, called race-condition-aware (RCA) clock skew scheduling, is proposed to determine the clock skew schedule by taking the race conditions into account. Our objective is not only to optimize the clock period, but also to heuristically minimize the required inserted delay. Compared with previous work, our approach has significant improvement in the time complexity.