IEEE Transactions on Computers
Understanding retiming through maximum average-delay cycles
Proceedings of the 3rd ACM symposium on Parallel algorithms and architectures
Clock Period Minimization of Non-Zero Clock Skew Circuits
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Race-condition-aware clock skew scheduling
Proceedings of the 42nd annual Design Automation Conference
Clock period minimization with minimum delay insertion
Proceedings of the 44th annual Design Automation Conference
Clock gating effectiveness metrics: Applications to power optimization
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
Delay insertion method in clock skew scheduling
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Although intentional clock skew can be utilized to reduce the clock period, its application in gated clock designs has not been well studied. A gated clock design includes both data paths and clock control paths, but conventional clock skew scheduling only focus on data paths. Based on that observation, in this paper, we propose an approach to perform the co-synthesis of data paths and clock control paths in a nonzero skew gated clock design. Our objective is to minimize the required inserted delay for working with the lower bound of the clock period (under clocking constraints of both data paths and clock control paths). Different from previous works, our approach can guarantee no clocking constraint violation in the presence of clock gating. Experimental results show our approach can effectively enhance the circuit speed with almost no penalty on the power consumption.