IEEE Transactions on Computers
Optimal clock skew scheduling tolerant to process variations
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Computational geometry: algorithms and applications
Computational geometry: algorithms and applications
Clock-tree routing realizing a clock-schedule for semi-synchronous circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Cycle time and slack optimization for VLSI-chips
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Clock skew scheduling for improved reliability via quadratic programming
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Introduction to Algorithms
Clock Scheduling and Clocktree Construction for High Performance ASICS
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Yield-Driven, False-Path-Aware Clock Skew Scheduling
IEEE Design & Test
Skew scheduling and clock routing for improved tolerance to process variations
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Clock Skew Scheduling Under Process Variations
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
An efficient merging scheme for prescribed skew clock routing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Yield driven skew scheduling method leads to a clock tree with much greater wire length and buffer number that is not acceptable by designer. Geometry based register position relationships are converted to skew constraints and are combined with timing constraints harmoniously. With the two kinds of skew constraints together, our algorithm solves the skew scheduling problem for both restrictions and gives safety margins for not only timing variations but clocktree wire variations. It makes the yield driven clock network realizable inpractical design. Experimental results show that our algorithm has 72.7% yield improvement then normal scheduling. In addition, the clock tree wire length and buffer number are reduced by 52.2% and 40.4% compared with previous yielddriven skew scheduling method.