IEEE Transactions on Computers
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ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
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ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Timing optimization through clock skew scheduling
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UST/DME: a clock tree router for general skew constraints
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Proceedings of the 2005 international symposium on Physical design
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Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
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Efficient generation of short and fast repeater tree topologies
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ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
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ACM Transactions on Algorithms (TALG)
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Journal of Experimental Algorithmics (JEA)
Retiming and time borrowing: optimizing high-performance pulsed-latch-based circuits
Proceedings of the 2009 International Conference on Computer-Aided Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
HLS-l: a high-level synthesis framework for latch-based architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An efficient merging scheme for prescribed skew clock routing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Approximation algorithms for network design and facility location with service capacities
APPROX'05/RANDOM'05 Proceedings of the 8th international workshop on Approximation, Randomization and Combinatorial Optimization Problems, and Proceedings of the 9th international conference on Randamization and Computation: algorithms and techniques
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In this paper we present a new method for clock schedulingand clocktree construction that improves the performance ofhigh-end ASICs significantly.First, we compute a clock schedule that yields the optimumcycle time and the best possible clock distribution with respectto early and late mode; in particular the number of criticaltests is minimized. Second, individual arrival time intervalsare computed for all endpoints of the clocktree. Finally, weconstruct a clocktree that realizes arrival times within theseintervals and exploits positive slacks to save power consumption.We demonstrate the superiority of our method to previousapproaches by experimental results on industrial ASICs withup to 194 000 registers and more than 160 clock domains. Weimproved the clock frequencies by 5-28% up to 1.033 GHz (in hardware).