IEEE Transactions on Computers
Analyzing cycle stealing on synchronous circuits with level-sensitive latches
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Critical paths in circuits with level-sensitive latches
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Minimum padding to satisfy short path constraints
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Timing optimization through clock skew scheduling
Timing optimization through clock skew scheduling
Skew-tolerant circuit design
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Design of a 10GHz clock distribution network using coupled standing-wave oscillators
Proceedings of the 40th annual Design Automation Conference
Clock Scheduling and Clocktree Construction for High Performance ASICS
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Multi-Domain Clock Skew Scheduling
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A timing analysis algorithm for circuits with level-sensitive latches
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multi-domain clock skew scheduling-aware register placement to optimize clock distribution network
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the 2011 international symposium on Physical design
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This paper describes a delay insertion method that improves the efficiency of clock skew scheduling. Clock skew scheduling is performed on synchronous circuits in order to improve the performance of a circuit; most often by permitting the circuit to operate at a lower clock period or by increasing the tolerance of the circuit against secondary order effects and process parameter variations. With clock skew scheduling, the original circuit topology is preserved while the clock distribution network is modified to satisfy an optimal clock schedule (set of clock signal arrival delays). The work presented here studies a circuit modification technique requiring systematic delay insertion within the circuit logic (delay insertion method) in order to improve the minimum clock period achieved through clock skew scheduling. The proposed delay insertion method is defined and demonstrated on both edge-triggered and level-sensitive synchronous circuits leading to average clock period improvements of 9% and 10%, respectively, over standard clock skew scheduling algorithms. Overall, the clock period improvements over zero clock skew, flip-flop based circuits are improved to 34% on average, both for the edge-triggered and level-sensitive designs of ISCAS'89 benchmark circuits.