IEEE Transactions on Computers
Cycle time and slack optimization for VLSI-chips
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Sequential Circuit Design Using Synthesis and Optimization
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Multi-Domain Clock Skew Scheduling
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Experimental analysis of the fastest optimum cycle ratio and mean algorithms
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Multi-level clustering for clock skew optimization
Proceedings of the 2009 International Conference on Computer-Aided Design
A fast heuristic algorithm for multidomain clock skew scheduling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Optimal multi-domain clock skew scheduling
Proceedings of the 48th Design Automation Conference
SmipRef: An efficient method for multi-domain clock skew scheduling
Integration, the VLSI Journal
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Clock skew scheduling is an effective technique in performance optimization of sequential circuits. However, with process variations, it becomes more difficult to reliably implement a wide spectrum of clock delays at the registers. Multi-domain clock skew scheduling is a good option to overcome this limitation. In this paper, we propose a practical method to efficiently and optimally solve this problem. A framework based on branch-and-bound is carefully designed to search for the optimal clocking domain assignment, and a greedy clustering algorithm is developed to quickly estimate the upper bound of cycle period for a given branch. Experiment results on ISCAS89 sequential benchmarks show both the optimality and efficiency of our method compared with previous works.