Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Precomputation-based sequential logic optimization for low power
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Symbolic synthesis of clock-gating logic for power optimization of synchronous controllers
ACM Transactions on Design Automation of Electronic Systems (TODAES)
BDS: a BDD-based logic optimization system
Proceedings of the 37th Annual Design Automation Conference
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Selective Clock-Gating for Low Power/Low Noise Synchronous Counters 1
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
BDD Decomposition for Efficient Logic Synthesis
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
A recursive paradigm to solve Boolean relations
Proceedings of the 41st annual Design Automation Conference
DDBDD: delay-driven BDD synthesis for FPGAs
Proceedings of the 44th annual Design Automation Conference
Automatic synthesis of clock gating logic with controlled netlist perturbation
Proceedings of the 45th annual Design Automation Conference
A novel sequential circuit optimization with clock gating logic
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Pulser gating: a clock gating of pulsed-latch circuits
Proceedings of the 16th Asia and South Pacific Design Automation Conference
On applying erroneous clock gating conditions to further cut down power
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Power optimization methodology for the IBM POWER7 microprocessor
IBM Journal of Research and Development
Novel pulsed-latch replacement based on time borrowing and spiral clustering
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
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In this paper we consider the problem of exploiting infeasible clock gating functions. Analysis of industrial designs reveals a large margin of potential for power saving based on clock gating functions that initially appear to be useless due to timing violation or excessive power consumption. We propose two optimization techniques for resurrecting such functions that can be used as a generic post-processing phase in an automatic clock gating tool. The first provides timing-aware approximation and the second aims at generating large gating domains by clustering similar clock gating functions. Our experimental results show that the combination of these two techniques yields an additional power saving of up to 78% in industrial designs.