Symbolic synthesis of clock-gating logic for power optimization of synchronous controllers
ACM Transactions on Design Automation of Electronic Systems (TODAES)
The budgeted maximum coverage problem
Information Processing Letters
Automatic synthesis of low-power gated-clock finite-state machines
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A scalable algorithm for RTL insertion of gated clocks based on ODCs computation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A novel sequential circuit optimization with clock gating logic
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Resurrecting infeasible clock-gating functions
Proceedings of the 46th Annual Design Automation Conference
Using SAT-based Craig interpolation to enlarge clock gating functions
Proceedings of the 48th Design Automation Conference
Timing Optimization in Sequential Circuit by Exploiting Clock-Gating Logic
ACM Transactions on Design Automation of Electronic Systems (TODAES)
| Hi-index | 0.00 |
Clock gating is the insertion of combinational logic along the clock path to prevent the unnecessary switching of registers and reduce dynamic power consumption. The conditions under which the transition of a register may be safely blocked can either be explicitly specified by the designer or detected automatically. We introduce a new method for automatically synthesizing these conditions in a way that minimizes netlist perturbation and is both timing- and physical-aware. Our automatic method is also scalable, utilizing simulation and satisfiability tests and necessitating no symbolic representation. On a set of benchmarks, our technique successfully reduces the dynamic clock power by 14.5% on average. Furthermore, we demonstrate how to apply a straightforward logic simplification to utilize resulting don't cares and reduce the logic by 7.0% on average.