Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
A threshold of ln n for approximating set cover
Journal of the ACM (JACM)
Stretching the Limits of Clock-Gating Efficiency in Server-Class Processors
HPCA '05 Proceedings of the 11th International Symposium on High-Performance Computer Architecture
Automatic synthesis of clock gating logic with controlled netlist perturbation
Proceedings of the 45th annual Design Automation Conference
Automatic synthesis of low-power gated-clock finite-state machines
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A counterexample-guided interpolant generation algorithm for SAT-based model checking
Proceedings of the 50th Annual Design Automation Conference
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Dynamic power saving is gaining its dominance in modern low power designs, while clock gating, which blocks unnecessary clock switching activities, is one of the most efficient approaches to reduce the dynamic power. In this paper, we exploit the interpolation technique in a SAT-based clock gating algorithm in order to grant a greater flexibility in enlarging the gating capabilities over the original gating candidates. We also developed several techniques to improve the runtime and memory usage of the clock gating algorithm, including a gating capability filter to reduce the number of formal SAT proofs, a dynamic backtracking limit controller to shorten the SAT runs, and a shrinking method to ease the final gate count overhead. The experimental results show that our proposed algorithm can gate up to 2X clock switches with less than 5% area overhead when compared to the state-of-the-art SAT-based clock gating methodology.