Stall cycle redistribution in a transparent fetch pipeline
Proceedings of the 2006 international symposium on Low power electronics and design
A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
A study of thread migration in temperature-constrained multicores
ACM Transactions on Architecture and Code Optimization (TACO)
A mathematical solution to power optimal pipeline design by utilizing soft edge flip-flops
Proceedings of the 13th international symposium on Low power electronics and design
Instruction-driven clock scheduling with glitch mitigation
Proceedings of the 13th international symposium on Low power electronics and design
Minimizing the energy cost of throughput in a linear pipeline by opportunistic time borrowing
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Low-power CMOS synchronous counter with clock gating embedded into carry propagation
IEEE Transactions on Circuits and Systems II: Express Briefs
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Temperature-aware task scheduling algorithm for soft real-time multi-core systems
Journal of Systems and Software
Integrated microarchitectural floorplanning and run-time controller for inductive noise mitigation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Using SAT-based Craig interpolation to enlarge clock gating functions
Proceedings of the 48th Design Automation Conference
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
GPUWattch: enabling energy optimizations in GPGPUs
Proceedings of the 40th Annual International Symposium on Computer Architecture
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Clock-gating has been introduced as the primary means of dynamic power management in recent high-end commercial microprocessors. The temperature drop resulting from active power reduction can result in additional leakage power savings in future processors. In this paper we first examine the realistic benefits and limits of clock-gating in current generation high-performance processors (e.g. of the POWER4驴 or POWER5驴 class).We then look beyond classical clock-gating: we examine additional opportunities to avoid unnecessary clocking in real workload executions. In particular, we examine the power reduction benefits of a couple of newly invented schemes called transparent pipeline clock-gating and elastic pipeline clock-gating.Based on our experiences with current designs, we try to bound the practical limits of clock gating efficiency in future microprocessors.