Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
The use of observability and external don't cares for the simplification of multi-level networks
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Dynamic variable ordering for ordered binary decision diagrams
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
BDD-based logic synthesis for LUT-based FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
DAG-Map: Graph-Based FPGA Technology Mapping for Delay Optimization
IEEE Design & Test
Logic synthesis for vlsi design
Logic synthesis for vlsi design
Bdd-based logic synthesis system
Bdd-based logic synthesis system
DAOmap: a depth-optimal area optimization mapping algorithm for FPGA designs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Improvements to technology mapping for LUT-based FPGAs
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
BDS: a BDD-based logic optimization system
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Resurrecting infeasible clock-gating functions
Proceedings of the 46th Annual Design Automation Conference
Global delay optimization using structural choices
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
Delay optimization using SOP balancing
Proceedings of the International Conference on Computer-Aided Design
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In this paper, we target FPGA performance optimization using a novel BDD (binary decision graph)-based synthesis approach. Most of previous works have focused on BDD size reduction during logic synthesis. In this work, we concentrate on delay reduction and conclude that there is a large optimization margin through BDD synthesis for FPGA performance optimization. Our contributions are threefold: (1) we propose a gain-based clustering and partial collapsing algorithm to prepare the initial design for BDD synthesis for better delay; (2) we use a technique named linear expansion for BDD decomposition, which in turn enables a dynamic programming algorithm to efficiently search through the optimization space for the BDD of each node in the clustered circuit; (3) we consider special decomposition scenarios coupled with linear expansion for further improvement on quality of results. Experimental results show that we can achieve a 95% gain in terms of network depths, and a 20% gain in terms of routed delay, with a 22% area overhead on average compared to a previous state-of-art BDD-based FPGA synthesis tool, BDS-pga.