Chortle: a technology mapping program for lookup table-based field programmable gate arrays
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Performance optimization using exact sensitization
DAC '94 Proceedings of the 31st annual Design Automation Conference
RASP: a general logic synthesis system for SRAM-based FPGAs
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
A new retiming-based technology mapping algorithm for LUT-based FPGAs
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
A new enhanced constructive decomposition and mapping algorithm
Proceedings of the 40th annual Design Automation Conference
Implicit enumeration of structural changes in circuit optimization
Proceedings of the 41st annual Design Automation Conference
DAOmap: a depth-optimal area optimization mapping algorithm for FPGA designs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Reducing structural bias in technology mapping
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
DDBDD: delay-driven BDD synthesis for FPGAs
Proceedings of the 44th annual Design Automation Conference
Combinational and sequential mapping with priority cuts
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Logic decomposition during technology mapping
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Robust Boolean reasoning for equivalence checking and functional property verification
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimizing Sequential Cycles Through Shannon Decomposition and Retiming
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Area-efficient FPGA logic elements: architecture and synthesis
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Delay optimization using SOP balancing
Proceedings of the International Conference on Computer-Aided Design
ABC: an academic industrial-strength verification tool
CAV'10 Proceedings of the 22nd international conference on Computer Aided Verification
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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This paper presents a fast global method for delay optimization after technology mapping. Timing analysis is used to identify timing-critical areas in the mapped network where new structures are synthesized to favor late-arriving signals. Unlike previous methods that make incremental local changes to the mapped network, the proposed method records many alternative structures and defers the final decision to the technology mapper. Experimental results for networks mapped into 6-input look-up tables (6-LUTs) show that the delay is, on average, improved 14% using a realistic delay library for LUTs with variable-pin delays and wire-delay estimation. The area penalty after the delay optimization is about 2% and can be eliminated by area-oriented resynthesis. When the algorithm is compared with DAOmap, the experimental results show 27% logic level reduction while the area is increased by only 1%. The algorithm is also fast and applicable to very large networks. The runtime of the proposed algorithm is 16x and 3x faster than DAOmap for large industrial and academic designs, respectively.