RISA: accurate and efficient placement routability modeling
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Algorithm 778: L-BFGS-B: Fortran subroutines for large-scale bound-constrained optimization
ACM Transactions on Mathematical Software (TOMS)
Multilevel hypergraph partitioning: applications in VLSI domain
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Modeling and minimization of routing congestion
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Estimating routing congestion using probabilistic analysis
Proceedings of the 2001 international symposium on Physical design
A new congestion-driven placement algorithm based on cell inflation
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
An effective congestion driven placement framework
Proceedings of the 2002 international symposium on Physical design
Congestion minimization during placement without estimation
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
mPL6: a robust multilevel mixed-size placement engine
Proceedings of the 2005 international symposium on Physical design
Routability-driven placement and white space allocation
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Congestion driven incremental placement algorithm for standard cell layout
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Architecture and details of a high quality, large-scale analytical placer
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Recursive Function Smoothing of Half-Perimeter Wirelength for Analytical Placement
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Fast and accurate routing demand estimation for efficient routability-driven placement
Proceedings of the conference on Design, automation and test in Europe
Congestion minimization during placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Congestion estimation during top-down placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Implementation and extensibility of an analytic placer
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multiobjective hypergraph-partitioning algorithms for cut and maximum subdomain-degree minimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Seeing the Forest and the Trees: Steiner Wirelength Optimization in Placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
CROP: fast and effective congestion refinement of placement
Proceedings of the 2009 International Conference on Computer-Aided Design
CRISP: congestion reduction by iterated spreading during placement
Proceedings of the 2009 International Conference on Computer-Aided Design
A study of routability estimation and clustering in placement
Proceedings of the 2009 International Conference on Computer-Aided Design
What makes a design difficult to route
Proceedings of the 19th international symposium on Physical design
Routability-driven analytical placement for mixed-size circuit designs
Proceedings of the International Conference on Computer-Aided Design
A size scaling approach for mixed-size placement
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Progress and challenges in VLSI placement research
Proceedings of the International Conference on Computer-Aided Design
A fast maze-free routing congestion estimator with hybrid unilateral monotonic routing
Proceedings of the International Conference on Computer-Aided Design
SRP: simultaneous routing and placement for congestion refinement
Proceedings of the 2013 ACM international symposium on International symposium on physical design
Routability-driven placement for hierarchical mixed-size circuit designs
Proceedings of the 50th Annual Design Automation Conference
Ripple 2.0: high quality routability-driven placement via global router integration
Proceedings of the 50th Annual Design Automation Conference
Optimization of placement solutions for routability
Proceedings of the 50th Annual Design Automation Conference
MIP-based detailed placer for mixed-size circuits
Proceedings of the 2014 on International symposium on physical design
Hi-index | 0.00 |
This paper presents an efficient technique for the estimation of the routed wirelength during global placement using the wire density of the net. The proposed method identifies congested regions of the chip and incorporates the model of the routed wirelength into the objective function in order to effectively alleviate these regions from congestion. The method is integrated in the analytical placement framework and the two-level structure improves the scalability of the placer and speeds up the algorithm. The proposed analytical placer provides the best-so-far average routed wirelength in the IBM version2 benchmark suite.