mPL6: a robust multilevel mixed-size placement engine

  • Authors:
  • Tony F. Chan;Jason Cong;Michalis Romesis;Joseph R. Shinnerl;Kenton Sze;Min Xie

  • Affiliations:
  • UCLA;UCLA;UCLA;UCLA;UCLA;UCLA

  • Venue:
  • Proceedings of the 2005 international symposium on Physical design
  • Year:
  • 2005

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Abstract

The most recent version of the mPL multilevel placement algorithm, mPL6, is reviewed. This version is derived from the mPL5 placer (ISPD05) and the Patoma floorplanner (ASPDAC05). It is also augmented by new techniques for detailed placement. As a result, it can handle mixed-size placement very effectively. First-choice clustering is used to construct a hierarchy of problem formulations. Generalized force-directed placement guides global placement at each level of the cluster hierarchy. Prior to interpolation of each coarse-level solution to its adjacent finer level, however, recursive, top-down displacement-minimizing floorplanning optimizes block orientations and checks that overlap can be removed at the current level. Where necessary, the floor-planner perturbs coarse-level solutions enough that legalization of the given placement can be assured. The resulting flow is scalable and robust, and it produces very low-wirelength solutions for known benchmark circuits.