FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Efficient circuit clustering for area and power reduction in FPGAs
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
An effective congestion driven placement framework
Proceedings of the 2002 international symposium on Physical design
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
Placement rent exponent calculation methods, temporal behaviour and FPGA architecture evaluation
Proceedings of the 2003 international workshop on System-level interconnect prediction
Architecture Adaptive Routability-Driven Placement for FPGAs (abstract only)
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Logic block clustering of large designs for channel-width constrained FPGAs
Proceedings of the 42nd annual Design Automation Conference
Congestion estimation and localization in fpgas:: a visual tool for interconnect prediction
Proceedings of the 2007 international workshop on System level interconnect prediction
Timing-driven nonuniform depopulation-based clustering
International Journal of Reconfigurable Computing - Special issue on selected papers from spl 2009 programmable logic and applications
Scalable and deterministic timing-driven parallel placement for FPGAs
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
MO-pack: many-objective clustering for FPGA CAD
Proceedings of the 48th Design Automation Conference
Net-length-based routability-driven power-aware clustering
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Integration of Net-Length Factor with Timing- and Routability-Driven Clustering Algorithms
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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FPGA device area is dominated by interconnect, so low-cost FPGA architectures often have reduced interconnect capacity. This limited routing capacity creates a hard channel width constraint that can make it difficult for CAD tools to successfully map a circuit into these devices. Instead of migrating a design to a high-cost, resource-rich architecture that is easier to route, we present a cheaper alternative: a fully automated CAD flow (Un/DoPack) that finds local regions of high interconnect demand and reduces it by spreading out the logic in that region. This is done by introducing whitespace in the form of empty logic elements (LEs) within the configurable logic blocks (CLBs) of the congested region. After spreading, the congested region occupies more routing channels and so obtains access to greater aggregate interconnect capacity. Although this has the side effect of using more CLBs, it has the advantage of lowering peak interconnect demands and making a previously-unroutable circuit routable. We also design a new set of synthetic benchmark circuits that model interconnect variation within a large design. Using these benchmarks, we show that circuits with high interconnect variation require FPGA devices to have large channel widths. However, since congestion of such circuits is localized, Un/DoPack is very good at reducing the peak demands of circuits with high interconnect variation. Our results suggest that even for an average Rent exponent of 0.62 (a modest value), a large variation of this exponent within a design will also require FPGAs to have large channel widths. Thus, it is crucial to study interconnect variation of benchmark circuits when designing lowcost FPGAs. Previous research studying interconnect properties focuses on average Rent exponent values of each design, but we believe new work should study variation as well. For circuits with high interconnect variation, we demonstrate that channel widths can be reduced by up to ~40% with only ~10% increase in area.