Improving the performance of the Kernighan-Lin and simulated annealing graph bisection algorithms
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
SIAM Journal on Numerical Analysis
Recent directions in netlist partitioning: a survey
Integration, the VLSI Journal
Quantified suboptimality of VLSI layout heuristics
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Multilevel circuit partitioning
DAC '97 Proceedings of the 34th annual Design Automation Conference
PROUD: A Sea-Of-Gates Placement Algorithm
IEEE Design & Test
Placement of circuit modules using a graph space approach
DAC '83 Proceedings of the 20th Design Automation Conference
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
DAC '82 Proceedings of the 19th Design Automation Conference
A combined force and cut algorithm for hierarchical VLSI layout
DAC '82 Proceedings of the 19th Design Automation Conference
Optimal partitioners and end-case placers for standard-cell layout
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Can recursive bisection alone produce routable placements?
Proceedings of the 37th Annual Design Automation Conference
Data path placement with regularity
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Free space management for cut-based placement
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
An algebraic multigrid solver for analytical placement with layout based clustering
Proceedings of the 40th annual Design Automation Conference
Faster and better global placement by a new transportation algorithm
Proceedings of the 42nd annual Design Automation Conference
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
New theoretical results on quadratic placement
Integration, the VLSI Journal
Integrated Computer-Aided Engineering
Cell placement on graphics processing units
Proceedings of the 20th annual conference on Integrated circuits and systems design
Maze routing Steiner trees with delay versus wire length tradeoff
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Quadratic placement with single-iteration linear system solver
Proceedings of the 24th symposium on Integrated circuits and systems design
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The "quadratic placement" methodology is rooted in [Module Placement Based on Resistive Network Optimization, Proud: A Sea-Of-Gate Placement Algorithm, A Combined Force and Cut Algorithm for Hierarchical VLSI Layout]and is reputedly used in many commercial and in-house tools forplacement of standard-cell and gate-array designs. The methodologyiterates between two basic steps: solving sparse systems oflinear equations, and repartitioning. This work dissects the implementationand motivations for quadratic placement. We firstshow that (i) Krylov subspace engines for solving sparse systemsof linear equations are more effective than the traditional successiveover-relaxation (SOR) engine [A Unified Approach to Partitioning and Placement] and (ii) order convergence criteriacan maintain solution quality while using substantially fewersolver iterations. We then discuss the motivations and relevanceof the quadratic placement approach, in the context of past and futurealgorithmic technology, performance requirements, and designmethodology. We provide evidence that the use of numerical linearsystems solvers with quadratic wirelength objective may be due tothe pre-1990's weakness of min-cut partitioners, i.e., numerical engineswere needed to provide helpful hints to min-cut partitioners.Finally, we note emerging methodology drivers in deep-submicrondesign that may require new placement approaches to the placement problem.