Placement of circuit modules using a graph space approach

Authors:
Kunio Fukunaga;Shoichiro Yamada;Harold S. Stone;Tamotsu Kasai
Affiliations:
Electrical and Computer Engineering Department, University of Massachusetts, Amherst, MA and Department of Electrical Engineering, Univesity of Osaka Prefecture, Sakai, Osaka, 591 Japan;Department of Electrical Engineering, Univesity of Osaka Prefecture, Sakai, Osaka, 591 Japan;Electrical and Computer Engineering Department, University of Massachusetts, Amherst, MA;Department of Electrical Engineering, Univesity of Osaka Prefecture, Sakai, Osaka, 591 Japan
Venue:
DAC '83 Proceedings of the 20th Design Automation Conference
Year:
1983

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Abstract

This paper deals with the problem of automated placement of electronic components in a circuit layout by using a graph-space approach. In this approach, the relationships of connections among modules in a given electronic circuit are represented by a hypergraph. Then by using a graph-space approach, the vertices (representing the modules) are mapped into the graph space such that the distance between vertices in the space reflects the weights (the number of wires) of edges between vertices of the original hypergraph. On the basis of this placement in graph-space, the modules are assigned to grids on the printed-circuit board so as to minimize the total wire length. Simulation results show this technique yields a better assignment than the one derived from a hand-optimized layout and from an accepted automated-design method.