Placement of circuit modules using a graph space approach
DAC '83 Proceedings of the 20th Design Automation Conference
Initial placement of gate arrays using least-squares methods
DAC '84 Proceedings of the 21st Design Automation Conference
Complexity theory and design automation
DAC '80 Proceedings of the 17th Design Automation Conference
Graph Theory with Applications to Engineering and Computer Science (Prentice Hall Series in Automatic Computation)
Efficient final placement based on nets-as-points
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
VLSI cell placement techniques
ACM Computing Surveys (CSUR)
A quadratic metric with a simple solution scheme for initial placement
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
On the relative placement and the transportation problem for standard-cell layout
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Analysis of placement procedures for VLSI standard cell layout
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Automatic placement a review of current techniques (tutorial session)
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Adaptive Cluster Growth (ACG): a new algorithm for circuit packing in rectilinear region
EURO-DAC '90 Proceedings of the conference on European design automation
Architecture-aware FPGA placement using metric embedding
Proceedings of the 43rd annual Design Automation Conference
An efficient heuristic for standard-cell placement
Integration, the VLSI Journal
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Placement algorithms for IC layout which are optimal are known to be NP-complete 5. As a result, heuristics such as pairwise-interchange techniques must be employed to generate satisfactory placements. Unfortunately, with these algorithms, there is generally no way of knowing just how far away the result is from optimum. With the quadratic metric used in this study, however, a useful absolute lower bound can be calculated for the score. Experiments show that with this metric, at least for homogenous interchangeable devices confined to a square grid, pairwise interchange suffices to move the placement very close to the global optimum over a range of 100 to 1600 devices; in particular, asymptotic approach to optimality is observed with increasing size. In addition, a theoretical model is developed which explains the observed deviation from optimality.