Introduction to algorithms
An empirical model for accurate estimation of routing delay in FPGAs
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Generic global placement and floorplanning
DAC '98 Proceedings of the 35th annual Design Automation Conference
Near-optimal placement using a quadratic objective function
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
P-Complete Approximation Problems
Journal of the ACM (JACM)
Timing-driven placement for FPGAs
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
An architecture-driven metric for simultaneous placement and global routing for FPGAs
Proceedings of the 37th Annual Design Automation Conference
Timing-driven placement for hierarchical programmable logic devices
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
Interconnect complexity-aware FPGA placement using Rent's rule
Proceedings of the 2001 international workshop on System-level interconnect prediction
Proceedings of the 2001 international symposium on Physical design
Lectures on Discrete Geometry
Graph Drawing by High-Dimensional Embedding
GD '02 Revised Papers from the 10th International Symposium on Graph Drawing
Fast timing-driven partitioning-based placement for island style FPGAs
Proceedings of the 40th annual Design Automation Conference
Multi-resource aware partitioning algorithms for FPGAs with heterogeneous resources
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Innovate or perish: FPGA physical design
Proceedings of the 2004 international symposium on Physical design
Performance-driven simultaneous placement and routing for FPGA's
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
FPGA Design Automation: A Survey
Foundations and Trends in Electronic Design Automation
Criticality history guided FPGA placement algorithm for timing optimization
Proceedings of the 18th ACM Great Lakes symposium on VLSI
FPGA placement using space-filling curves: Theory meets practice
ACM Transactions on Embedded Computing Systems (TECS)
A3MAP: architecture-aware analytic mapping for networks-on-chip
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Improving FPGA placement with dynamically adaptive stochastic tunneling
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
StarPlace: A new analytic method for FPGA placement
Integration, the VLSI Journal
A3MAP: Architecture-aware analytic mapping for networks-on-chip
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on verification challenges in the concurrent world
Embedding-based placement of processing element networks on FPGAs for physical model simulation
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
An efficient and effective analytical placer for FPGAs
Proceedings of the 50th Annual Design Automation Conference
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Since performance on FPGAs is dominated by the routing architecture rather than wirelength, we propose a new ar-chitecture-aware approach to initial FPGA placement that models the relationship between performance and the routing grid, using concepts from graph embedding and metric geometry. Our approach, CAPRI, can be viewed as an embedding of a graph representing the netlist into a metric space that is representative of the FPGA. First, we develop an analytic metric of distance that models delays along the FPGA routing grid. We then embed a netlist into the defined metric space using matrix projections and online bipartite matching. Experimental comparisons with the popular FPGA tool, VPR, show that with CAPRI's initial solution, the resulting placements show median improvements of 10% in critical path delays for the larger MCNC benchmarks. Total placement runtime is also improved by 2x on average.