Performance-driven placement of cell based IC's
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Prime: a timing-driven placement tool using a piecewise linear resistive network approach
DAC '93 Proceedings of the 30th international Design Automation Conference
Generic global placement and floorplanning
DAC '98 Proceedings of the 35th annual Design Automation Conference
Timing-driven placement for FPGAs
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
An architecture-driven metric for simultaneous placement and global routing for FPGAs
Proceedings of the 37th Annual Design Automation Conference
Timing-driven placement for hierarchical programmable logic devices
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
Fast placement approaches for FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
Hardware-assisted simulated annealing with application for fast FPGA placement
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
A novel net weighting algorithm for timing-driven placement
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Fast timing-driven partitioning-based placement for island style FPGAs
Proceedings of the 40th annual Design Automation Conference
Sensitivity guided net weighting for placement driven synthesis
Proceedings of the 2004 international symposium on Physical design
An LP-based methodology for improved timing-driven placement
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Architecture-aware FPGA placement using metric embedding
Proceedings of the 43rd annual Design Automation Conference
New timing and routability driven placement algorithms for FPGA synthesis
Proceedings of the 17th ACM Great Lakes symposium on VLSI
An efficient quadratic placement based on search space traversing technology
Integration, the VLSI Journal
Force-Directed Methods for Generic Placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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We present an efficient timing-driven placement algorithm for FPGAs. Our major contribution is a criticality history guided (CHG) approach that can simultaneously reduce the critical path delay and computation time. The proposed approach keeps track of the timing criticality history of each edge and utilizes this information to effectively guide the placer. We also present a cooling schedule that optimizes both timing and run time when combined with the CHG method. The proposed algorithm is applied to the 20 largest MCNC benchmark circuits. Experimental results show that compared with VPR, our algorithm yields an average of 21.7% reduction (maximum 45.8%) in the critical path delay and it runs 2.2X fasterthan VPR. In addition, our approach outperforms other algorithms discussed in the literature in both delay and run time.