Performance-driven placement of cell based IC's
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Prime: a timing-driven placement tool using a piecewise linear resistive network approach
DAC '93 Proceedings of the 30th international Design Automation Conference
RISA: accurate and efficient placement routability modeling
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Generic global placement and floorplanning
DAC '98 Proceedings of the 35th annual Design Automation Conference
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Timing-driven placement for FPGAs
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Fast placement approaches for FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
Hardware-assisted simulated annealing with application for fast FPGA placement
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
A novel net weighting algorithm for timing-driven placement
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Chip layout optimization using critical path weighting
DAC '84 Proceedings of the 21st Design Automation Conference
DAOmap: a depth-optimal area optimization mapping algorithm for FPGA designs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
An LP-based methodology for improved timing-driven placement
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Optimal simultaneous mapping and clustering for FPGA delay optimization
Proceedings of the 43rd annual Design Automation Conference
Criticality history guided FPGA placement algorithm for timing optimization
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Improving simulated annealing-based FPGA placement with directed moves
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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We present new timing and congestion driven FPGA placement algorithms with minimal runtime overhead. By predicting the post-routing critical edges and estimating congestion accurately, our algorithms simultaneously reduce the critical path delay and the minimum number of routing tracks. The core of our algorithm consists of a criticality history record of connection edges and a congestion map. This approach is applied to the 20 largest MCNC benchmark circuits. Experimental results show that compared with VPR [1], our algorithms yield an average of 8.1% reduction (maximum 30.5%) in the critical path delay and 5% reduction in channel width. Meanwhile, the average runtime of our algorithms is only 2.3X as of VPR's.