Innovate or perish: FPGA physical design

Authors:
Taraneh Taghavi;Soheil Ghiasi;Abhishek Ranjan;Salil Raje;Majid Sarrafzadeh
Affiliations:
University of California, Los Angeles, CA;University of California, Los Angeles, CA;Hier Design Inc.;Hier Design Inc.;University of California, Los Angeles, CA
Venue:
Proceedings of the 2004 international symposium on Physical design
Year:
2004

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Abstract

The recent past has seen a tremendous increase in the size of design circuits that can be implemented in a single FPGA. The size and complexity of modern FPGAs has far outpaced the innovations in FPGA physical design. The problems faced by FPGA designers are similar in nature to those that preoccupy ASIC designers, namely, interconnect delays and design management. However, this paper will show that a simple re-targeting of ASIC physical design methodologies and algorithms to the FPGA domain will not suffice. We will show that several well researched problems in the ASIC world need new problem formulations and algorithms research to be useful for today's FPGAs. Partitioning, floorplanning, placement, delay estimation schemes are only some of the topics that need complete overhaul. We will give problem formulations, motivated by experimental results, for some of these topics as applicable in the FPGA domain.