Compression-relaxation: a new approach to performance driven placement for regular architectures
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Timing-constrained layout algorithms for symmetrical field-programmable gate arrays
Timing-constrained layout algorithms for symmetrical field-programmable gate arrays
Hierarchical timing-driven partitioning and placement for symmetrical FPAGS
Hierarchical timing-driven partitioning and placement for symmetrical FPAGS
Combining technology mapping and placement for delay-optimization in FPGA designs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
A timing driven N-way chip and multi-chip partitioner
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
An evolutionary approach to timing driven FPGA placement
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
Innovate or perish: FPGA physical design
Proceedings of the 2004 international symposium on Physical design
Multi-Million Gate FPGA Physical Design Challenges
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Interconnect capacitance estimation for FPGAs
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Power estimation techniques for FPGAs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Architecture-aware FPGA placement using metric embedding
Proceedings of the 43rd annual Design Automation Conference
A novel approach to the placement and routing problems for field programmable gate arrays
Applied Soft Computing
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We present an empirical routing delay model for estimating interconnection delays in FPGAs. We assume that the routing delay is a function of interPLC distances, circuit size, fanout of the net and routing congestion in the channel. We performed extensive simulations of various circuits to generate a sufficiently large dataset. Our method estimates delays by reading the average value tables and interpolating the values, if necessary. We present a rigorous statistical justification of this delay model. Our results show that our method predicts the delays within 20% of actual and it far outperforms all other existing techniques.