An introduction to neural computing
An introduction to neural computing
Introduction to artificial neural systems
Introduction to artificial neural systems
A new global routing algorithm for FPGAs
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
New performance-driven FPGA routing algorithms
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
An empirical model for accurate estimation of routing delay in FPGAs
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Proceedings of the 1997 international symposium on Physical design
AAAI '98/IAAI '98 Proceedings of the fifteenth national/tenth conference on Artificial intelligence/Innovative applications of artificial intelligence
FPGA routing architecture: segmentation and buffering to optimize speed and density
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Genetic algorithms for VLSI design, layout & test automation
Genetic algorithms for VLSI design, layout & test automation
An evolutionary approach to timing driven FPGA placement
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
Parallel algorithms for FPGA placement
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
Timing-driven routing for symmetrical array-based FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Runtime and quality tradeoffs in FPGA placement and routing
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
Genetic Algorithms in Search, Optimization and Machine Learning
Genetic Algorithms in Search, Optimization and Machine Learning
Interconnect resource-aware placement for hierarchical FPGAs
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
FPGA global routing based on a new congestion metric
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
An Analysis of the Interacting Roles of Population Size and Crossover in Genetic Algorithms
PPSN I Proceedings of the 1st Workshop on Parallel Problem Solving from Nature
A Study of Crossover Operators in Genetic Programming
ISMIS '91 Proceedings of the 6th International Symposium on Methodologies for Intelligent Systems
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
A New Switch Block for Segmented FPGAs
FPL '99 Proceedings of the 9th International Workshop on Field-Programmable Logic and Applications
Routing on Switch Matrix Multi-FPGA Systems
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
An Algorithm for Dynamically Reconfigurable FPGA Placement
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
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This paper presents an artificial neural network (ANN) based parallel evolutionary solution to the placement and routing problems for field programmable gate arrays (FPGAs). The concepts of artificial neural networks are utilized for guiding the parallel genetic algorithm to intelligently transform a set of initial populations of randomly generated solutions to a final set of populations that contain solutions approximating the optimal one. The fundamental concept of this paper lies in capturing the various intuitive strategies of the human brain into neural networks, which may help the genetic algorithm to evolve its population in a more lucrative manner. A carefully chosen fitness function acts in the capacity of a yardstick to appraise the quality of each ''chromosome'' to aid the selection phase. In conjunction with the migration phase and the chosen fitness function various genetic operators are employed, to expedite the transformation of the initial population towards the final solution. The suggested algorithms have been implemented on a 12-node SGI Origin-2000 platform using the message passing interface (MPI) standard and the neural network utilities provided by MAT Lab software. The results obtained by executing the same are extremely encouraging, especially for circuits with very large number of nets.