A novel approach to the placement and routing problems for field programmable gate arrays
Applied Soft Computing
Temporal floorplanning using the three-dimensional transitive closure subGraph
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Complexity of 3-D floorplans by analysis of graph cuboidal dual hardness
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Abstract: In this paper, we introduce a new placement problem movitated by the Dynamically Reconfigurable FPGA (DRFPGA) architectures. Unlike traditional placement, the problem for DRFPGAs must consider the precedence constraints among logic components. For the placement, we develop an effective metric that can consider wirelength, register requirement, and power consumption simultaneously. With the considerations of the new metric and the precedence constraints, we then present a three-stage scheme of partitioning, initial placement generation, and placement refinement to solve the new placement problem. Experimental results show that our placement scheme with the new metric achieves respective improvements of 17.2%, 27.0%, and 35.9% in wirelength, the number of registers, and power consumption requirements, compared with the list scheduling method.