A linear algorithm for embedding planar graphs using PQ-trees
Journal of Computer and System Sciences
Regular edge labeling of 4-connected plane graphs and its applications in graph drawing problems
Theoretical Computer Science
A linear algorithm to find a rectangular dual of a planar triangulated graph
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Embedding planar graphs on the grid
SODA '90 Proceedings of the first annual ACM-SIAM symposium on Discrete algorithms
DAC '84 Proceedings of the 21st Design Automation Conference
The complexity of theorem-proving procedures
STOC '71 Proceedings of the third annual ACM symposium on Theory of computing
An Algorithm for Dynamically Reconfigurable FPGA Placement
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
Physical Design of the "2.5D" Stacked System
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Physical Design for 3D System on Package
IEEE Design & Test
Simultaneous power and thermal integrity driven via stapling in 3D ICs
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Placement of 3D ICs with thermal and interlayer via considerations
Proceedings of the 44th annual Design Automation Conference
| Hi-index | 0.00 |
Interconnect dominated electronic design stimulates a demand for developing circuits on the third dimension, leading to 3-D integration. Recent advances in chip fabrication technology enable 3-D circuit manufacturing. However, there is still a possible barrier of design complexity in exploiting 3-D technologies. This article discusses the impact of migrating from 2-D to 3-D on the difficulty of floorplanning and placement. By looking at a basic formulation of the graph cuboidal dual problem, we show that the 3-D cases and the 3-layer 2.5-D cases are fundamentally more difficult than the 2-D cases in terms of computational complexity. By comparison among these cases, the intrinsic complexity in 3-D floorplan structures is revealed in the hard-to-decide relations between topological connections and geometrical contacts. The results show possible challenges in the future for physical design and CAD of 3-D integrated circuits.