An algorithm for finding a rectangular dual of a planar graph for use in area planning for VLSI integrated circuits.

  • Authors:
  • Krzysztof Kozminski;Edwin Kinnen

  • Affiliations:
  • Department of Electrical Engineering, The University of Rochester, Rochester, NY;Department of Electrical Engineering, The University of Rochester, Rochester, NY

  • Venue:
  • DAC '84 Proceedings of the 21st Design Automation Conference
  • Year:
  • 1984

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Abstract

An O(n2) algorithm for finding a rectangular dual of a planar triangulated graph is presented. In practice, almost linear running times have been observed. The algorithm is useful for solving area planning problems in VLSI IC design.