An O-tree representation of non-slicing floorplan and its applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Classical floorplanning harmful?
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Introduction to Algorithms
Corner block list: an effective and efficient topological representation of non-slicing floorplan
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
DAC '84 Proceedings of the 21st Design Automation Conference
Proceedings of the 2004 international symposium on Physical design
ACG-Adjacent Constraint Graph for General Floorplans
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Are floorplan representations important in digital design?
Proceedings of the 2005 international symposium on Physical design
DeFer: deferred decision making enabled fixed-outline floorplanner
Proceedings of the 45th annual Design Automation Conference
Linear constraint graph for floorplan optimization with soft blocks
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Fixed-outline floorplanning: enabling hierarchical design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Twin binary sequences: a nonredundant representation for general nonslicing floorplan
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper describes a new floorplanning approach called Constrained Adjacency Graph (CAG) that helps exploring adjacency in floorplans. CAG extends the previous adjacency graph approaches by adding explicit adjacency constraints to the graph edges. After sufficient and necessary conditions of CAG are developed based on dissected floorplans, CAG is extended to handle general floorplans in order to improve area without changing the adjacency relations dramatically. These characteristics are currently utilized in a randomized greedy improvement heuristic for wire length optimization. The results show that better floorplans are found with much less running time for problems with 100 to 300 modules in comparison to a simulated annealing floorplanner based on sequence pairs.