Efficient floorplan area optimization
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Optimal aspect ratios of building blocks in VLSI
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
A new algorithm for floorplan design
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
A linear algorithm to find a rectangular dual of a planar triangulated graph
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Linear ordering and application to placement
DAC '83 Proceedings of the 20th Design Automation Conference
Optimization techniques for two-dimensional placement
DAC '84 Proceedings of the 21st Design Automation Conference
DAC '84 Proceedings of the 21st Design Automation Conference
The planar package planner for system designers
DAC '82 Proceedings of the 19th Design Automation Conference
DAC '82 Proceedings of the 19th Design Automation Conference
Timing influenced force directed floorplanning
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Performance driven floorplanning for FPGA based designs
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
Macro Block Based FPGA Floorplanning
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Combinatorial approaches to QoS scheduling in multichannel infrastructure wireless networks
WICON '06 Proceedings of the 2nd annual international workshop on Wireless internet
A generic, formal language-based methodology for hierarchical floorplanning-placement
Computer Languages, Systems and Structures
A novel thermal optimization flow using incremental floorplanning for 3D ICs
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
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An analytical method for general floorplan design and optimization is proposed. This method is based on a mixed integer programming model and application of a standard mathematical software. The method allows arbitrary combinations of rigid and flexible modules. Various objective functions such as chip area, interconnection length, timing delays or any combinations of them are permitted. Routing space is estimated by the global router. Experimental data are provided.