on VLSI CAD tools and applications
on VLSI CAD tools and applications
An analytical approach to floorplan design and optimization
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
A source-level dynamic analysis methodology and tool for high-level synthesis
ISSS '97 Proceedings of the 10th international symposium on System synthesis
Automatic parallel control structures in SequenceL
Software—Practice & Experience
A Genetic Algorithm for the Synthesis of Structured Data Paths
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
A Floorplanning-Synthesis Methodology For Multiple Chip Module Design
Journal of Integrated Design & Process Science
Integrating expert knowledge in environmental site characterization
IEEE Transactions on Systems, Man, and Cybernetics, Part C: Applications and Reviews
Manufacturing feature recognition toward integration with processplanning
IEEE Transactions on Systems, Man, and Cybernetics, Part B: Cybernetics
IEEE Transactions on Systems, Man, and Cybernetics, Part A: Systems and Humans
A parallel implementation of the SCAN language
Computer Languages
A new method for floor planning using topological constraint reduction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal floorplan area optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal realizations of floorplans [VLSI layout]
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Genetic algorithms for VLSI micro-cell layout area optimization based on binary tree
ACST '08 Proceedings of the Fourth IASTED International Conference on Advances in Computer Science and Technology
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Floorplanning in 2-D or 3-D space is always a difficult and time consuming problem for automated manufacturing, storaging, civil engineering design and especially for the physical layout design cycle of the chip design automation. In particular, the physical layout cycle itself consists of several steps, such as partitioning, floorplanning, placement, synthesis, routing, and compaction, where the right placement of the appropriate components is the most important element of performance. In this paper, a generic floor-planning methodology is presented by offering a good solution to such problems. The methodology is based on the hierarchical cooperation of two context-free languages (Scan and Geometria). In order to achieve an acceptable planning, the Scan language defines the partitioning of the floor area and the global acquisition strategy (scan patterns) for the placement of the macro-blocks. On the other hand, the Geometria language deals with the local synthesis of the block under the constraints superimposed by global scan patterns. The results obtained by this methodology are very promising in comparison with other floorplanning methodologies.