Hand-in-hand verification of high-level synthesis
Proceedings of the 17th ACM Great Lakes symposium on VLSI
A VLSI DESIGN DESIGN-SYNTHESIS METHODOLOGY AT THE TRANSISTOR LAYOUT LEVEL
Journal of Integrated Design & Process Science
A generic, formal language-based methodology for hierarchical floorplanning-placement
Computer Languages, Systems and Structures
Workload driven power domain partitioning
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
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The technique presented here achieves simultaneous optimization of schedule time and data path component cost within a structured data path architecture, using a genetic algorithm. The data path architecture has been designed to overcome the problem of random interconnections between data path components by buses, which makes subsequent physical design more difficult. The data path is organized as architectural blocks (A-blocks), some or none global memory units, all interconnected by a few global buses. Each A-block has a local functional unit, local memory elements and local interconnections. The operations are scheduled such that the required data transfers are achieved using the few available global buses, and their interconnections to the A-blocks. The synthesis is guided by user specified architectural parameters, such as the number of A-blocks and global buses. The benchmark examples synthesized by this technique compare well with those synthesized by other commonly known synthesis techniques.