Macro-block placement using efficient 2-D compaction
Proceedings of the 1991 University of California/Santa Cruz conference on Advanced research in VLSI
Automatic logic synthesis techniques for digital systems
Automatic logic synthesis techniques for digital systems
A source-level dynamic analysis methodology and tool for high-level synthesis
ISSS '97 Proceedings of the 10th international symposium on System synthesis
High-Level VLSI Synthesis
A Genetic Algorithm for the Synthesis of Structured Data Paths
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
A Floorplanning-Synthesis Methodology For Multiple Chip Module Design
Journal of Integrated Design & Process Science
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This paper presents a VLSI design synthesis methodology based on the Geometria language. Geometria is a context-free language, which has the ability of floorplanning, compaction and automated synthesis of functional blocks at various levels of a VLSI integration, starting from the transistor level. The Geometria methodology used in this paper deals with the design synthesis of VLSI circuit layout. More specifically it accepts various user's inputs such as stick diagram, circuit schematics, Boolean expression, netlists, or natural language text expressions, and produces automatically the desirable VLSI layout. One of the major characteristics of Geometria is that it is an automated process for VLSI layout placement and synthesis of blocks at various levels of integration.