System partitioning to maximize sleep time
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Genetic algorithms in solving graph partitioning problem
IEA/AIE '99 Proceedings of the 12th international conference on Industrial and engineering applications of artificial intelligence and expert systems: multiple approaches to intelligent systems
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Genetic algorithms for graph partitioning and incremental graph partitioning
Proceedings of the 1994 ACM/IEEE conference on Supercomputing
Design Space Exploration for Data Path Synthesis
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
A Genetic Algorithm for the Synthesis of Structured Data Paths
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
A Low-Power Partitioning Methodology by Maximizing Sleep Time and Minimizing Cut Nets
IWSOC '05 Proceedings of the Fifth International Workshop on System-on-Chip for Real-Time Applications
The challenges of implementing fine-grained power gating
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Fixed-outline thermal-aware 3D floorplanning
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
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This paper presents a formulation for the problem of partitioning the set of components on a power rail of a low power integrated circuit into power domains based on the usage patterns given by an application specific workload. We present an analysis of the underlying problem, proving that the problem is NP-complete. We propose a greedy algorithm for this problem and compare its solutions with a more exhaustive search based on a genetic algorithm formulation. It is shown through empirical evaluation that the greedy algorithm is in general a well suited algorithm for this problem.