Microarchitectural techniques for power gating of execution units
Proceedings of the 2004 international symposium on Low power electronics and design
Benefits and Costs of Power-Gating Technique
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Low Power Methodology Manual: For System-on-Chip Design
Low Power Methodology Manual: For System-on-Chip Design
A low-power ASIP for IEEE 802.15.4a ultra-wideband impulse radio baseband processing
Proceedings of the Conference on Design, Automation and Test in Europe
Workload driven power domain partitioning
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
| Hi-index | 0.00 |
Power consumption in digital systems, especially in portable devices, is a crucial design factor. Due to downscaling of technology, dynamic switching power is not the only relevant source of power consumption anymore as power dissipation caused by leakage currents increases. Even though power gating is a seemingly simple method for reducing the leakage power, the implications of introducing power gating to a design have to be analyzed in detail. We present an extensive analysis of the impact of fine-grained power gating on the overall power consumption. The presented results are based on the analysis of an actual implementation of power gating in the datapath of a very long instruction word (VLIW) processor. The extracted power consumption values clearly demonstrate that the overhead of power gating is, in contrary to the analysis found in previous publication, not determined by the energy required to switch a power domain on. Rather, it is determined by the energy consumption of additionally required modules. We show that, for the break-even point case, about 2/3 of the energy overhead is caused by the isolation cells, about 1/3 by the control modules, and only roughly 1% by the energy to switch a power domain on.