Bristle Blocks: A silicon compiler
DAC '79 Proceedings of the 16th Design Automation Conference
An analytic optimization technique for placement of macro-cells
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
VLSI cell placement techniques
ACM Computing Surveys (CSUR)
An analytical approach to floorplan design and optimization
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
The Silc silicon compiler: language and features
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
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Present VLSI synthesis programs typically characterized as silicon compilers employ a predefined floorplan and fixed placement of functional elements. Significant broadening of the areas of application and more effective utilization of silicon space can be obtained by using a general placement of functionally clustered elements rather than a fixed floorplan. In this paper we present a new mathematical optimization technique to achieve a two-dimensional placement. The two-dimensional placement problem is the most important part of the hierarchical placement approach being considered by GTE Laboratories for its SilC Silicon Compiler. This paper describes a method of solving the placement problem in a mathematical form and an algorithm for optimization. The construction of a mathematical model and the use of optimization techniques represent the main distinction from heuristic placement procedures. The optimization technique guarantees a feasible placement at each iteration. It is also possible to determine at each stage how close the solution is to the optimum, and therefore the process may be stopped when the result is sufficiently close to optimum. A small, illustrative example of a two-dimensional placement problem was considered.