VLSI cell placement techniques
ACM Computing Surveys (CSUR)
PathFinder: a negotiation-based performance-driven router for FPGAs
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Performance of a new annealing schedule
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Trading quality for compile time: ultra-fast placement for FPGAs
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
New parallelization and convergence results for NC: a negotiation-based FPGA router
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Timing-driven routing for symmetrical array-based FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Accelerating Boolean Satisfiability with Configurable Hardware
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
A fast, inexpensive and scalable hardware acceleration technique for functional simulation
Proceedings of the 39th annual Design Automation Conference
Hardware-assisted simulated annealing with application for fast FPGA placement
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
A Placement/Routing Approach for FPGA Accelerators
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Fast timing-driven partitioning-based placement for island style FPGAs
Proceedings of the 40th annual Design Automation Conference
Engineering details of a stable force-directed placer
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A novel approach to the placement and routing problems for field programmable gate arrays
Applied Soft Computing
Static and Dynamic Memory Footprint Reduction for FPGA Routing Algorithms
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
FPGA placement using space-filling curves: Theory meets practice
ACM Transactions on Embedded Computing Systems (TECS)
Discrete cooperative particle swarm optimization for FPGA placement
Applied Soft Computing
Improving simulated annealing-based FPGA placement with directed moves
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Intermediate fabrics: virtual architectures for circuit portability and fast placement and routing
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Improving FPGA placement with dynamically adaptive stochastic tunneling
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Towards scalable FPGA CAD through architecture
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
Run-time generation of partial FPGA configurations
Journal of Systems Architecture: the EUROMICRO Journal
A low-overhead interconnect architecture for virtual reconfigurable fabrics
Proceedings of the 2012 international conference on Compilers, architectures and synthesis for embedded systems
BPR: fast FPGA placement and routing using macroblocks
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
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Many applications of FPGAs, especially logic emulation and custom computing, require the quick placement and routing of circuit designs. In these applications, the advantages FPGA-based systems have over software simulation are diminished by the long run-times of current CAD software used to map the circuit onto FPGAs. To improve the run-time advantage of FPGA systems, users may be willing to trade some mapping quality for a reduction in CAD tool runtimes. In this paper, we seek to establish how much quality degradation is necessary to achieve a given runtime improvement. For this purpose, we implemented and investigated numerous placement and routing algorithms for FPGAs. We also developed new tradeoff-oriented algorithms, where a tuning parameter can be used to control this quality vs. runtime tradeoff. We show how different algorithms can achieve different points within this tradeoff spectrum, as well as how a single algorithm can be tuned to form a curve in the spectrum. We demonstrate that the algorithms vary widely in their tradeoffs, with the fastest algorithm being 8x faster than the slowest, and the highest quality algorithm being 5x better than the least quality algorithm. Compared to the commercial Xilinx CAD tools, we can achieve a 3x speed-up by allowing 1.27x degradation in quality, and a factor of 1.6x quality improvement with 2x slowdown.