Discrete cooperative particle swarm optimization for FPGA placement

Authors:
Mohammed El-Abd;Hassan Hassan;Mohab Anis;Mohamed S. Kamel;Mohamed Elmasry
Affiliations:
University of Waterloo, ECE Department, 200 University Av. W., Waterloo, Ontario, N2L3G1, Canada;Actel Corporation, 2061 Stierlin Court, Mountain View, CA 94043, USA;University of Waterloo, ECE Department, 200 University Av. W., Waterloo, Ontario, N2L3G1, Canada;University of Waterloo, ECE Department, 200 University Av. W., Waterloo, Ontario, N2L3G1, Canada;University of Waterloo, ECE Department, 200 University Av. W., Waterloo, Ontario, N2L3G1, Canada
Venue:
Applied Soft Computing
Year:
2010

Citing 7
Cited 3

VLSI cell placement techniques

ACM Computing Surveys (CSUR)
Runtime and quality tradeoffs in FPGA placement and routing

FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
Architecture and CAD for Deep-Submicron FPGAs

Architecture and CAD for Deep-Submicron FPGAs
A linear-time heuristic for improving network partitions

DAC '82 Proceedings of the 19th Design Automation Conference
Geometric particle swarm optimization

Journal of Artificial Evolution and Applications - Particle Swarms: The Second Decade
A Cooperative approach to particle swarm optimization

IEEE Transactions on Evolutionary Computation
Efficiently solving general weapon-target assignment problem by genetic algorithms with greedy eugenics

IEEE Transactions on Systems, Man, and Cybernetics, Part B: Cybernetics

A revision algorithm for invalid encodings in concurrent formation of overlapping coalitions

Applied Soft Computing
A discrete particle swarm optimization algorithm with self-adaptive diversity control for the permutation flowshop problem with blocking

Applied Soft Computing
An approach using particle swarm optimization and bottleneck heuristic to solve hybrid flow shop scheduling problem

Applied Soft Computing

Quantified Score

Hi-index	0.00

Visualization

Abstract

Particle swarm optimization (PSO) is a stochastic optimization technique that has been inspired by the movement of birds. On the other hand, the placement problem in field programmable gate arrays (FPGAs) is crucial to achieve the best performance. Simulated annealing algorithms have been widely used to solve the FPGA placement problem. In this paper, a discrete PSO (DPSO) version is applied to the FPGA placement problem to find the optimum logic blocks and IO pins locations in order to minimize the total wire-length. Moreover, a co-operative version of the DPSO (DCPSO) is also proposed for the FPGA placement problem. The problem is entirely solved in the discrete search space and the proposed implementation is applied to several well-known FPGA benchmarks with different dimensionalities. The results are compared to those obtained by the academic versatile place and route (VPR) placement tool, which is based on simulated annealing. Results show that both the DPSO and DCPSO outperform the VPR tool for small and medium-sized problems, with DCPSO having a slight edge over the DPSO technique. For higher-dimensionality problems, the algorithms proposed provide very close results to those achieved by VPR.