Optional linear arrangement of circuit components
Advances in VLSI and Computer Systems
Simulated annealing for VLSI design
Simulated annealing for VLSI design
VLSI cell placement techniques
ACM Computing Surveys (CSUR)
Recent directions in netlist partitioning: a survey
Integration, the VLSI Journal
Space-filling curves and their use in the design of geometric data structures
Theoretical Computer Science - Special issue: Latin American theoretical informatics
Algorithm 781: generating Hilbert's space-filling curve by recursion
ACM Transactions on Mathematical Software (TOMS)
Multilevel hypergraph partitioning: applications in VLSI domain
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
New approximation techniques for some ordering problems
Proceedings of the ninth annual ACM-SIAM symposium on Discrete algorithms
Divide-and-conquer approximation algorithms via spreading metrics
Journal of the ACM (JACM)
Runtime and quality tradeoffs in FPGA placement and routing
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
Design and analysis of physical design algorithms
Proceedings of the 2001 international symposium on Physical design
Approximation algorithms
Theory of Computation: A Primer
Theory of Computation: A Primer
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Tabu Search: Ultra-Fast Placement for FPGAs
FPL '99 Proceedings of the 9th International Workshop on Field-Programmable Logic and Applications
Fast timing-driven partitioning-based placement for island style FPGAs
Proceedings of the 40th annual Design Automation Conference
Random Projection: A New Approach to VLSI Layout
FOCS '98 Proceedings of the 39th Annual Symposium on Foundations of Computer Science
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
Multi-Million Gate FPGA Physical Design Challenges
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Annealing placement by thermodynamic combinatorial optimization
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Handbook of Mathematical Functions, With Formulas, Graphs, and Mathematical Tables,
Handbook of Mathematical Functions, With Formulas, Graphs, and Mathematical Tables,
Architecture-aware FPGA placement using metric embedding
Proceedings of the 43rd annual Design Automation Conference
New theoretical results on quadratic placement
Integration, the VLSI Journal
An improved approximation ratio for the minimum linear arrangement problem
Information Processing Letters
FPGA Design Automation: A Survey
Foundations and Trends in Electronic Design Automation
On the metric properties of discrete space-filling curves
IEEE Transactions on Image Processing
Embedding-based placement of processing element networks on FPGAs for physical model simulation
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
d-dimensional arrangement revisited
Information Processing Letters
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Research in VLSI placement, an NP-hard problem, has branched in two different directions. The first one employs iterative heuristics with many tunable parameters to produce a near-optimal solution but without theoretical guarantee on its quality. The other one considers placement as a graph-embedding problem and designs approximation algorithms with provable bounds on the quality of the solution. In this article, we aim at unifying the above two directions. First, we extend the existing approximation algorithms for graph embedding in 1D and 2D grid to those for hypergraphs, which typically model circuits to be placed on a FPGA. We prove an approximation bound of O(d &sqrt;log n log log n) for 1D, that is, linear arrangement and O(d log n log log n) for the 2D grid, where d is the maximum degree of hyperedges and n, the number of vertices in the hypergraph. Next, we propose an efficient method based on linear arrangement of the CLBs and the notion of space-filling curves for placing the configurable logic blocks (CLBs) of a netlist on island-style FPGAs with an approximation guarantee of O(4&sqrt;log n &sqrt;kd log log n), where k is the number of nets. For the set of FPGA placement benchmarks, the running time is near linear in the number of CLBs thus allowing for scalability towards large circuits. We obtained a 33× speed-up, on average, with only 1.31× degradation in the quality of the solution compared to that produced by the popular FPGA tool VPR, thereby demonstrating the suitability of this very fast method for FPGA placement, with a provable performance guarantee.