Simulated annealing for VLSI design
Simulated annealing for VLSI design
Combinatorial algorithms for integrated circuit layout
Combinatorial algorithms for integrated circuit layout
Finding good approximate vertex and edge partitions is NP-hard
Information Processing Letters
A faster strongly polynomial minimum cost flow algorithm
Operations Research
Modeling hypergraphs by graphs with the same mincut properties
Information Processing Letters
Random walks on weighted graphs and applications to on-line algorithms
Journal of the ACM (JACM)
Recent directions in netlist partitioning: a survey
Integration, the VLSI Journal
Algorithms for large-scale flat placement
DAC '97 Proceedings of the 34th annual Design Automation Conference
DAC '97 Proceedings of the 34th annual Design Automation Conference
Generic global placement and floorplanning
DAC '98 Proceedings of the 35th annual Design Automation Conference
Spectral partitioning with multiple eigenvectors
Discrete Applied Mathematics - Special volume on VLSI
Improved approximations of crossings in graph drawings
STOC '00 Proceedings of the thirty-second annual ACM symposium on Theory of computing
Divide-and-conquer approximation algorithms via spreading metrics
Journal of the ACM (JACM)
Local search for final placement in VLSI design
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Random Projection: A New Approach to VLSI Layout
FOCS '98 Proceedings of the 39th Annual Symposium on Foundations of Computer Science
A polylogarithmic approximation of the minimum bisection
FOCS '00 Proceedings of the 41st Annual Symposium on Foundations of Computer Science
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
New Approximation Techniques for Some Linear Ordering Problems
SIAM Journal on Computing
Faster and better global placement by a new transportation algorithm
Proceedings of the 42nd annual Design Automation Conference
GORDIAN: VLSI placement by quadratic programming and slicing optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Geometric quadrisection in linear time, with application to VLSI placement
Discrete Optimization
FPGA placement using space-filling curves: Theory meets practice
ACM Transactions on Embedded Computing Systems (TECS)
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Current tools for VLSI placement are based either on quadratic placement, or on min-cut heuristics, or on simulated annealing. For the most complex chips with millions of movable objects, algorithms based on quadratic placement seem to yield the best results within reasonable time. In this paper, we prove several new theoretical results on quadratic placement. We point out connections to random walks and electrical networks. Moreover, we argue that quadratic placement has, in contrast to the other approaches, some well-defined stability properties. Finally, we consider the question how to choose the weights of the clique edges representing a multiterminal net optimally.