Fast module mapping and placement for datapaths in FPGAs
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Fast integrated tools for circuit design with FPGAs
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
A fast routability-driven router for FPGAs
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Trading quality for compile time: ultra-fast placement for FPGAs
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Runtime and quality tradeoffs in FPGA placement and routing
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
| Hi-index | 0.00 |
In this paper, we propose an algorithm of placement and routing for FPGA accelerators. The algorithm is designed to reduce the time for placement and routing of the register transfer level codes generated by a C to HDL compiler. In the codes generated from algorithms written in programming languages, only the limited kinds of operations are used, and they have strong sequentiality from top to bottom. Therefore, in our approach, all circuits for operations in the codes are placed and routed sequentially from top to bottom without finding global optimal placement in order to reduce the computation time. Experiments on some circuits showed good results. The execution time for placement/ routing of about 100K gate circuits is a few seconds and more than 70% of CLBs can be utilized.