An evolutionary approach to timing driven FPGA placement

Authors:
R. Venkatraman;Lalit M. Patnaik
Affiliations:
Centre for Electronics Design and Technology, Indian Institute of Science, Bangalore, India;Microprocessor Applications Laboratory, Indian Institute of Science, Bangalore, India
Venue:
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
Year:
2000

Citing 7
Cited 1

Genetic algorithms: A Survey

Computer
A delay driven FPGA placement algorithm

EURO-DAC '94 Proceedings of the conference on European design automation
Timing driven placement for large standard cell circuits

DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
An empirical model for accurate estimation of routing delay in FPGAs

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Genetic Algorithms in Search, Optimization and Machine Learning

Genetic Algorithms in Search, Optimization and Machine Learning
Timing-driven placement for regular architectures

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Performance-driven simultaneous placement and routing for FPGA's

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

A novel approach to the placement and routing problems for field programmable gate arrays

Applied Soft Computing

Quantified Score

Hi-index	0.00

Visualization

Abstract

We propose a novel evolutionary approach to the problem of timing-driven FPGA placement. The method used is evolutionary programming (EP) with incremental position encoded in the population. This uses considerably less memory compared to a method with direct position-encoding for members of the population. The algorithm has been implemented in C++, and the results on MCNC benchmark circuits are presented. The results are superior to those obtained using conventional Simulated Annealing (SA) based approach. The results of an EP-SA approach using the proposed evolutionary programming method are also presented.