Optimal orientations of cells in slicing floorplan designs
Information and Control
Simulated annealing for VLSI design
Simulated annealing for VLSI design
Efficient floorplan area optimization
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
An optimal algorithm for floorplan area optimization
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
DAC '93 Proceedings of the 30th international Design Automation Conference
Timing driven placement in interaction with netlist transformations
Proceedings of the 1997 international symposium on Physical design
Rectilinear block placement using sequence-pair
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Topology constrained rectilinear block packing for layout reuse
ISPD '98 Proceedings of the 1998 international symposium on Physical design
On the behavior of congestion minimization during placement
ISPD '99 Proceedings of the 1999 international symposium on Physical design
A timing-driven soft-macro resynthesis method in interaction with chip floorplanning
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A new algorithm for floorplan design
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Integrated floorplanning and interconnect planning
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Buffer block planning for interconnect-driven floorplanning
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
A min-cut placement algorithm for general cell assemblies based on a graph representation
DAC '79 Proceedings of the 16th Design Automation Conference
Innovate or perish: FPGA physical design
Proceedings of the 2004 international symposium on Physical design
Multi-Million Gate FPGA Physical Design Challenges
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Accurate and efficient flow based congestion estimation in floorplanning
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
3D module placement for congestion and power noise reduction
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Design flow and methodology for 50M gate ASIC
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
| Hi-index | 0.00 |
We propose fresher looks into already existing hierarchical partitioning based floor-plan design methods and their relevance in providing faster alternatives to conventional approaches. We modify the existing partitioning based floor-planner to handle congestion and timing. We also explore the applicability of traditional Sizing Theorem for combining two modules based on their sizes and inter connecting wirelength. The results show that our floorplanning approach can produce floor-plans hundred times faster and at the same time achieving better quality (on average 20% better wirelength, better congestion and better timing optimization) than that of pure Simulated Annealing based floor-planner.