Rectangle-packing-based module placement
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
The ISPD98 circuit benchmark suite
ISPD '98 Proceedings of the 1998 international symposium on Physical design
An algorithm for optimal decoupling capacitor sizing and placement for standard cell layouts
Proceedings of the 2002 international symposium on Physical design
Fast Hierarchical Floorplanning with Congestion and Timing Control
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Floorplanning with power supply noise avoidance
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Decoupling capacitance allocation and its application to power-supply noise-aware floorplanning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Three-dimensional Integrated Circuit Design
Three-dimensional Integrated Circuit Design
Congestion-aware power grid optimization for 3D circuits using MIM and CMOS decoupling capacitors
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Power delivery design for 3-D ICs using different through-silicon via (TSV) technologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Thermal-aware P/G TSV planning for IR drop reduction in 3D ICs
Integration, the VLSI Journal
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3D packaging via System-On-Package (SOP) is a viable alternative to System-On-Chip (SOC) to meet the rigorous requirements of today's mixed signal system integration. In this work, we propose a 3D module and decap (decoupling capacitance) placement algorithm that simultaneously reduces the power supply noise and wire congestion. We provide efficient algorithms for 3D power supply noise and congestion analysis to guide our 3D module placement process. In addition, we allocate white spaces around the modules that require decaps to suppress the power supply noise while minimizing the area overhead. In our experimentation, we achieve improvements in both decap amount and congestion with only small increase in area, wirelength, and runtime.