Introduction to algorithms
Network flows: theory, algorithms, and applications
Network flows: theory, algorithms, and applications
Power supply noise analysis methodology for deep-submicron VLSI chip design
DAC '97 Proceedings of the 34th annual Design Automation Conference
A new algorithm for floorplan design
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Integrated floorplanning and interconnect planning
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Decoupling capacitance allocation for power supply noise suppression
Proceedings of the 2001 international symposium on Physical design
Integrated power supply planning and floorplanning
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Simulation and optimization of the power distribution network in VLSI circuits
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Hierarchical analysis of power distribution networks
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
3D module placement for congestion and power noise reduction
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
CAD for nanometer silicon design challenges and success
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Nanoelectronic circuits and systems
Supply Voltage Degradation Aware Analytical Placement
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Timing-aware power noise reduction in layout
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Stochastic power/ground supply voltage prediction and optimization via analytical placement
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Floorplanning with IR-drop consideration
ICOSSSE'05 Proceedings of the 4th WSEAS/IASME international conference on System science and simulation in engineering
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With today's advanced integrated circuits (ICs) manufacturing technology in deep submicron (DSM) environment, we can integrate entire electronic systems on a single chip (SoC). However, without careful power supply planning in layout, the design of chips will suffer from mostly signal integrity problems including IR-drop, ΔI noise, and IC reliability. Postroute methodologies in solving signal integrity problem have been applied but they will cause a long turn-around time, which adds costly delays to time-to-market. In this paper, we study the problem of power supply noise avoidance as early as in floorplanning stage. We show that the noise avoidance in power supply planning problem can be formulated as a constrained maximum flow problem and present an efficient yet effective heuristic to handle the problem. Experimental results are encouraging. With slight increase of total wirelength, we achieve almost no-IR-drop requirement violation and 46.6% of improvement on ΔI noise constraint violation compared with a previous approach.