Floorplanning with IR-drop consideration

Authors:
Jian Chen;Chonghong Zhao;Dian Zhou;Xiaofang Zhou
Affiliations:
ASIC & System State-key Lab, Microelectronics Department, Fudan University, Shanghai, P. R. China;ASIC & System State-key Lab, Microelectronics Department, Fudan University, Shanghai, P. R. China;Department of Electrical Engineering, School of Engineering and Computer Sciences, The University of Texas at Dallas, Richardson, TX;ASIC & System State-key Lab, Microelectronics Department, Fudan University, Shanghai, P. R. China
Venue:
ICOSSSE'05 Proceedings of the 4th WSEAS/IASME international conference on System science and simulation in engineering
Year:
2005

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Abstract

As technology advances, with supply voltage decrease and power density increase modern chips suffer more seriously IR-drop problem. In this paper IR-drop constraint is considered in floorplanning stage in order to solve problem in the early stages of physical design and shorten time to market. First a fast model with some extend of accuracy is proposed to quantify the IR-drop of a block. And then selection strategy in simulating annealing based on the model being introduced. The experiments show that the algorithm proposed in this paper can reduce the chip average IR-drop and maximum IR-drop effectively and only brings a little tradeoff in area.