Proceedings of the 1997 international symposium on Physical design
A module area estimator for VLSI layout
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Clustering based simulated annealing for standard cell placement
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
A timing-driven soft-macro resynthesis method in interaction with chip floorplanning
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Fast floorplanning for effective prediction and construction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
PEPPER-a timing driven early floorplanner
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Fast Hierarchical Floorplanning with Congestion and Timing Control
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
A method for area estimation of data-path in high level synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multilevel circuit partitioning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An integrated logical and physical design flow for deep submicron circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Budgeting-free hierarchical design method for large scale and high-performance LSIs
Proceedings of the 43rd annual Design Automation Conference
Fixed-outline floorplanning: enabling hierarchical design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents a methodology for full chip RTL timing closure for very large ASIC's. The methodology is based on the concept of a "Silicon Virtual Prototype". The methodology is based on the scalable technique of clustering and cluster placement and leverages the tight integration between the algorithms by means of a common, unified data model.