Understanding and addressing the impact of wiring congestion during technology mapping
Proceedings of the 2002 international symposium on Physical design
The scaling challenge: can correct-by-construction design help?
Proceedings of the 2003 international symposium on Physical design
Bounding the efforts on congestion optimization for physical synthesis
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Quality of EDA CAD Tools: Definitions, Metrics and Directions
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Design flow and methodology for 50M gate ASIC
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
NCXplore: a design space exploration framework of temporal encoding for on-chip serial interconnects
International Journal of High Performance Systems Architecture
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This paper presents a set of techniques and a new design flow to be used in the synthesis of high-performance deep-submicron logic circuits. The design flow consists of circuit partitioning into tree like clusters, floorplanning, global routing, and timing analysis/budgeting steps, followed by simultaneous technology mapping and linear placement of each cluster. The strength of this approach lies in the dynamic programming-based algorithms used in performing simultaneous technology mapping and linear placement of the logic clusters. The two algorithms we propose, one for exact total (gate plus routing) area minimization and the other for total (gate plus routing) delay minimization, generate a set of noninferior solutions for each cluster enabling designers to perform tradeoffs between total-area and total-delay. Experimental results on large benchmarks prove the effectiveness of the proposed flow